On modeling and control of multilevel converters and PLL algorithms.
Martínez Montejano, Misael Francisco
DirectorEscobar Valderrama, Gerardo
"The present thesis is focuses in the study of the multilevel converters and the the phaselocked loop algorithms. In the first five chapters, two of the main topologies of multilevel converters are studied, namely, diode clamped multilevel converter (NPC) and cascaded H-bridge multilevel converter (HB). First, a model is obtained that described the dynamics of the three level NPC converter used in a synchronous rectifier application. The highly nonlinear model, originally in abc-coordinates, is also expressed in its ®¯°-coordinates. Special attention is given to the °-component of the control input, which represents a degree of freedom crucial for the balancing of the capacitors voltages. Then, based on this model, it is presented an adaptive controller that guarantees regulation and balance of the output capacitors voltages, as well as a close to unity power factor. Next, the modeling and the control design processes are presented for a cascade H-bridge single-phase multilevel converter used as a shunt active filter. Crucial for the developments is the transformation of the model in terms of the sum and the difference of the squares of the capacitors voltages. Moreover, it is shown that, while the current tracking problem and the regulation problem depend on the sum of the injected voltages, the balance depends on the difference between them. It is also presented a controller for the cascade H-bridge three-phase multilevel converter used as a shunt active filter. Based on the proposed mathematical model, the controller is designed to compensate harmonic distortion and reactive power due to a nonlinear distorting load. Simultaneously, the controller guarantees regulation and balance of all capacitor voltages. The idea behind the controller is to allow distortion of the current reference during the transients to guarantee regulation and balance of the capacitors voltages. The chapters 6 and 7 of the thesis deals with the design of phase-locked loop (PLL) algorithms. Although PLLs have been widely used in many electronic applications, the PLL presented here is of special interest in the synchronization of power electronic equipment coupled with the electric network. In particular, the presented PLL has been designed to work in fixed reference frame coordinates, and thus the proposed algorithm is referred as fixed reference frame PLL (FRF-PLL)."
DescriptionTesis (Doctorado en Control y Sistemas Dinámicos)
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